Self-aligned silicide (Salicide) processes have been widely used to lower resistances of gate and source/drain regions of transistors. Generally, a Salicide process is a method of simultaneously forming a silicide layer on a polysilicon gate electrode and on an active region of a silicon substrate. A Salicide process can lower the contact resistance and the sheet resistance.
FIG. 1 is a cross-sectional view illustrating a conventional MOS transistor having a lightly doped drain (LDD) region. Referring to FIG. 1, field regions 4 are formed on a semiconductor substrate 2 to define an active region therebetween. A gate stack, including a gate insulation layer 6, a gate electrode 8, and a gate silicide layer 16a, are formed on a predetermined region of the active region. A gate spacer 12 is formed on both sidewalls of the gate stack. A lightly doped region 10 is formed in the semiconductor substrate 2 under the gate spacer 12 by, for example, implanting ions into the substrate 2 prior to formation of the gate spacer 12. A heavily doped region 14 is formed in the active region of the semiconductor substrate 2 adjacent to the gate spacer 12. A silicide layer 16b is formed on a surface of the heavily doped region 14.
The lightly doped region 10 can be self-aligned to the gate stack between a channel region that underlies the gate stack and the heavily doped region 14. The lightly doped region 10 allows an electric field between the source/drain region and the channel region to be decreased which may prevent or reduce the rapid acceleration of carriers emitted from the source (i.e., hot carrier effects).